This paper presents a new power-efficient and high-speed voltage level shifter. In the proposed structure, the existing contentions at the internal nodes are reduced using auxiliary transistors and feedback networks, leading to a significant reduction in the transition delay and the energy dissipation of the circuit. Moreover, since the critical nodes are completely charged up to the high supply voltage, the static or standby power dissipation is also decreased. The proposed circuit is designed and simulated with a 0.18-mu m CMOS process for the target voltage level translation from 0.4V to 1.8V. According to the post-layout simulation results, the proposed voltage level shifter exhibits a propagation delay of 7 ns and a power dissipation of 78 nW. Moreover, the leakage power of the circuit is only 150 pW.