A 170μW Image Signal Processor Enabling Hierarchical Image Recognition for Intelligence at the Edge
2020
Abstract
We propose an ultra-low power (ULP) Image Signal Processor (ISP) that performs on-the-fly in-processing frame (de)compression and hierarchical event recognition to exploit the temporal and spatial sparsity in an image sequence to achieve a 16× imaging system energy gain. The ISP is fabricated in 40 nm CMOS and consumes only 170 μW at 5 fps for neural network-based intruder detection and 192× compressed image recording.
Details
Title
A 170μW Image Signal Processor Enabling Hierarchical Image Recognition for Intelligence at the Edge
Author(s)
An, Hyochan ; Venkatesan, Siddharth ; Schiferl, Sam ; Wesley, Tim ; Zhang, Qirui ; Wang, Jingcheng ; Choo, Kyojin ; Liu, Shiyu ; Liu, Bowen ; Li, Ziyun ; Zhong, Hengfei ; Gong, Luyao ; Blaauw, David ; Dreslinski, Ronald ; Sylvester, Dennis ; Kim, Hun Seok
Published in
2020 IEEE Symposium on VLSI Circuits proceedings
Pages
1-2
Conference
IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, 16-19 June 2020
Date
2020
Publisher
IEEE
Other identifier(s)
DOI: https://doi.org/10.1109/VLSICircuits18222.2020.9162810
Laboratories
MSIC-LAB
Record Appears in
Scientific production and competences > STI - School of Engineering > IEM - Institut d'Electricité et de Microtechnique > MSIC-LAB - Mixed-Signal Integrated Circuits Lab
Scientific production and competences > EPFL Partners > Neuchâtel Campus > MSIC-LAB - Mixed-Signal Integrated Circuits Lab
Peer-reviewed publications
Work outside EPFL
Conference Papers
Scientific production and competences > EPFL Partners > Neuchâtel Campus > MSIC-LAB - Mixed-Signal Integrated Circuits Lab
Peer-reviewed publications
Work outside EPFL
Conference Papers
Record creation date
2022-04-01